Method and system for supporting multiple cache configurations

ABSTRACT

A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

BACKGROUND OF THE INVENTION

[0001] Referring to FIG. 1, an electrical coupling network between astatic random access memory 20 a (hereinafter “SRAM 20a”) and a staticrandom access memory 20 b (hereinafter “SRAM 20b”) is shown. SRAM 20 aand SRAM 20 b are identical memory devices. Specifically, both SRAM 20 aand SRAM 20 bhave an identical pin arrangement including seven (7) rowsand seventeen (17) columns of pins. The first column of pins are shownin FIG. 1. In the first column of pins, SRAM 20 a includes two (2)output power supply pins 21 a and 27 a, and SRAM 20 b includes two (2)output power supply pins 21 b and 27 b. Also in the first column ofpins, SRAM 20 a includes four (4) synchronous address input pins 22 a,23 a, 25 a, and 26 a, and SRAM 20 b includes four (4) synchronousaddress input pins 22 b, 23 b, 25 b, and 26 b. Pin 24 a of SRAM 20 a andpin 24 b of SRAM 20 b are not utilized.

[0002] In support of four (4) cache configurations, SRAM 20 a is mountedto a front side of a processor card 10, and SRAM 20 b is mounted to arear side of processor card 10. SRAM 20 a and SRAM 20 b are positionedwith an alignment of pin 21 a and pin 27 b, an alignment of pin 22 a andpin 26 b, an alignment of pin 23 a and pin 25 b, an alignment of pin 24a and pin 24 b, an alignment of pin 25 a and pin 23 b, an alignment ofpin 26 a and pin 22 b, and an alignment of pin 27 a and pin 21 b.

[0003] Pin 22 a and pin 22 b are functionally equivalent andelectrically coupled via a conductor 28 a within processor card 10 toconcurrently receive a first address bit signal from a microprocessor.Pin 23 a and pin 23 b are functionally equivalent and electricallycoupled via a conductor 28 b within processor card 10 to concurrentlyreceive a second address bit signal from the microprocessor. Pin 25 aand pin 25 b are functionally equivalent and electrically coupled via aconductor 28 c within processor card 10 to concurrently receive a thirdaddress bit signal from the microprocessor. Pin 26 a and pin 26 b arefunctionally equivalent and electrically coupled via a conductor 28 dwithin processor card 10 to concurrently receive a fourth address bitsignal from the microprocessor. The four (4) address bits signal areselectively provided by the microprocessor as a function of a selectedcache configuration.

[0004] A drawback associated with the aforementioned electricalcouplings as shown is the length of conductors 28 a-28 d tends toestablish a maximum frequency at which the microprocessor caneffectively and efficiently control SRAM 20 a and SRAM 20 b, and theestablished maximum frequency can be significantly lower than a desiredoperating frequency of the microprocessor. The computer industry istherefore continually striving to improve upon the electrical couplingbetween the synchronous address input pins of SRAM 20 a and SRAM 20 bwhereby a maximum frequency at which a microprocessor can effectivelyand efficiently control SRAM 20 a and SRAM 20 b matches a desiredoperating frequency of the microprocessor. The computer industry is alsocontinually striving to improve upon the electrical communication of aselected cache configuration from a microprocessor to the synchronousaddress input pins of SRAM 20 a and SRAM 20 b.

FIELD OF THE INVENTION

[0005] The present invention generally relates to computer hardwaremounted upon a processor card, and in particular to an electricalcoupling between memory components for supporting multiple cacheconfigurations and an electrical communication from a microprocessor tothe memory components for selecting one of the supported multiple cacheconfigurations.

SUMMARY OF THE INVENTION

[0006] One form of the present invention is a processor card having afirst memory device and a second memory device mounted thereon. Thefirst memory device includes a first address pin and a second addresspin. The second memory device includes a third address pin and a fourthaddress pin. The first address pin of the first memory device and thethird address pin of the second memory device are functionallyequivalent address pins. The second address pin of the first memorydevice and the fourth address pin are functionally equivalent addresspins. The first address pin of the first memory device and the fourthaddress pin of the second memory device are electrically coupled tothereby concurrently receive a first address bit signal. The secondaddress pin of the first memory device and the third address pin of thesecond memory device are electrically coupled to thereby concurrentlyreceive a second address bit signal.

[0007] Another form of the present invention is a system including afirst memory device, a second memory device, and a microprocessor. Thefirst memory device includes a first address pin and a second addresspin. The second memory device includes a third address pin and a fourthaddress pin. The first address pin of the first memory device and thethird address pin of the second memory device are functionallyequivalent address pins. The second address pin of the first memorydevice and the fourth address pin are functionally equivalent addresspins. The microprocessor is operable to concurrently provide a firstaddress bit signal to first address pin of the first memory device andthe fourth address pin of the second memory device. The microprocessoris further operable to concurrently provide a first address bit signalto second address pin of the first memory device and the third addresspin of the second memory device.

[0008] The foregoing and other features and advantages of the inventionwill become further apparent from the following detailed description ofthe presently preferred embodiments, read in conjunction with theaccompanying drawings. The detailed description and drawings are merelyillustrative of the invention rather than limiting, the scope of theinvention being defined by the appended claims and equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a fragmented side view of a processor card having a pairof static random accesses memories mounted thereon with an electricalcoupling of synchronous address pins as known in the art;

[0010]FIG. 2 is view of the FIG. 1 processor card and FIG. 1 staticrandom accesses memories with an electrical coupling of synchronousaddress pins in accordance with the present invention;

[0011]FIG. 3A is a general block diagram of a first embodiment of amicroprocessor in accordance with the present invention;

[0012]FIG. 3B is a general block diagram of a second embodiment of amicroprocessor in accordance with the present invention; and

[0013]FIG. 3C is a general block diagram of one embodiment of amicroprocessor in accordance with the present invention.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0014] Referring to FIG. 2, SRAM 20 a and SRAM 20 b are mounted uponprocessor card 10 as previously described in connection with FIG. 1. Inaccordance with the present invention, pin 22 a and pin 26 b areelectrically coupled via a conductor 29 a within processor card 10 toconcurrently receive a first address bit signal. Pin 23 a and pin 25 bare electrically coupled via a conductor 29 b within processor card 10to concurrently receive a second address bit signal. Pin 25 a and pin 23b are electrically coupled via a conductor 29 c within processor card 10to concurrently receive a third address bit signal. Pin 26 a and pin 22b are electrically coupled via a conductor 29 d within processor card 10to concurrently receive a fourth address bit signal. The length of theconductors 29 a-29 d facilitate an effective and efficient operation ofSRAM 20 a and SRAM 20 b over a wide range of operating frequencies of amicroprocessor.

[0015] Referring to FIG. 3A, a microprocessor 30 in accordance with thepresent invention for selecting between two (2) of the four (4) cacheconfigurations supported by SRAM 20 a and SRAM 20 b is shown.Microprocessor 30 includes main logic units 31 for interpreting andexecuting operating and application programs as would occur to oneskilled in the art. Microprocessor 30 further includes a controller 32and a multiplexer 33. Address bus 32 a and address bus 32 b provideelectrical communication between controller 32 and multiplexer 33.Address bus 32 a and address bus 32 b each have two (2) address lines.Multiplexer 33 has an address bus 33 a with a first address lineelectrically coupled to pin 22 a (FIG. 2) and pin 26 b (FIG. 2), and asecond address line electrically coupled to pin 26 a (FIG. 2) and pin 22b (FIG. 2). The following Table 1 exemplary illustrates an address bitlogic utilized by main logic units 31 for electrically communicating aselected cache configuration between an 8 Mbyte cache and a 16 Mbytecache to SRAM 20 a and SRAM 20 b. TABLE 1 FIRST SECOND ADDRESS CACHEADDRESS ADDRESS BUS SIZE LINE (MSB) LINE (LSB) 32a  8 Mbyte net2 net232b 16 Mbyte net1 net2

[0016] Still referring to FIG. 3A, microprocessor 30 further comprises aconfiguration register 34. Configuration register 34 provides a controlsignal to multiplexor 33 via a control bus 34 a in response to aselection signal from main logic units 31 via a data bus 31 a. Theselection signal is indicative of a selected cache configuration by mainlogic units 31 during an initial boot of microprocessor 30. The controlsignal is indicative of the address bus that corresponds to the selectedcache configuration. Consequently, multiplexor 33 provides theappropriate address signals via address bus 33 a to SRAM 20 a and SRAM20 b in response to the selection signal. For example, when theselection signal indicates the 16 Mbyte cache has been selected duringan initial boot of microprocessor 30, pin 22 a and pin 26 b concurrentlyreceive address signal net1, and pin 26 a and pin 22 b concurrentlyreceive address signal net2 as indicated by Table 1.

[0017] Referring to FIG. 3B, a microprocessor 40 in accordance with thepresent invention for selecting between three (3) of the four (4) cacheconfigurations supported by SRAM 20 a and SRAM 20 b is shown.Microprocessor 40 includes main logic units 41 for interpreting andexecuting operating and application programs as would occur to oneskilled in the art. Microprocessor 40 further includes a controller 42and a multiplexer 43. Address bus 42 a, address bus 42 b, and addressbus 42 c provide electrical communication between controller 42 andmultiplexer 43. Address bus 42 a address bus 42 b, and address bus 42 ceach have three (3) address lines. Multiplexer 43 has an address bus 43a with a first address line electrically coupled to pin 22 a (FIG. 2)and pin 26 b (FIG. 2), a second address line electrically coupled to pin26 a (FIG. 2) and pin 22 b (FIG. 2), and a third address lineelectrically coupled to pin 23 a (FIG. 2) and pin 25 b (FIG. 2). Thefollowing Table 2 exemplary illustrates the address bit logic utilizedby main logic units 41 for electrically communicating a selected cacheconfiguration between a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbytecache to SRAM 20 a and SRAM 20 b. TABLE 2 FIRST SECOND THIRD ADDRESSCACHE ADDRESS ADDRESS ADDRESS BUS SIZE LINE (MSB) LINE LINE (LSB) 32a  4Mbyte net3 net3 net3 32b  8 Mbyte net2 net2 net3 32c 16 Mbyte net1 net2net3

[0018] Still referring to FIG. 3B, microprocessor 40 further comprises aconfiguration register 44. Configuration register 44 provides a controlsignal to multiplexor 43 via a control bus 44 a in response to aselection signal from main logic units 41 via a data bus 41 a. Theselection signal is indicative of a selected cache configuration by mainlogic units 41 during an initial boot of microprocessor 40. The controlsignal is indicative of the address bus that corresponds to the selectedcache configuration. Consequently, multiplexor 43 provides theappropriate address signals via address bus 43 a to SRAM 20 a and SRAM20 b in response to the selection signal. For example, when theselection signal indicates the 8 Mbyte cache has been selected, pin 22 aand pin 26 b concurrently receive address signal net2, pin 26 a and pin22 b concurrently receive address signal net2, and pin 23 a and pin 25 bconcurrently receive address signal net3 as indicated by Table 2.

[0019] Referring to FIG. 3C, a microprocessor 50 in accordance with thepresent invention for selecting between all four (4) cacheconfigurations supported by SRAM 20 a and SRAM 20 b is shown.Microprocessor 50 includes main logic units 51 for interpreting andexecuting operating and application programs as would occur to oneskilled in the art. Microprocessor 50 further includes a controller 52and a multiplexer 53. Address bus 52 a, address bus 52 b, address bus 52c, and address bus 52 d provide electrical communication betweencontroller 52 and multiplexer 53. Address bus 52 a address bus 52 b,address bus 52 c, and address bus 52 d each have four (4) address lines.Multiplexer 53 has an address bus 53 a with a first address lineelectrically coupled to pin 22 a (FIG. 2) and pin 26 b (FIG. 2), asecond address line electrically coupled to pin 26 a (FIG. 2) and pin 22b (FIG. 2), a third address line electrically coupled to pin 23 a (FIG.2) and pin 25 b (FIG. 2), and a fourth address line electrically coupledto pin 23 b (FIG. 2) and pin 25 a (FIG. 2). The following Table 3exemplary illustrates the address bit logic utilized by main logic units51 for electrically communicating a selected cache configuration betweena 2 Mbyte cache, a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbyte cacheto SRAM 20 a and SRAM 20 b. TABLE 3 FIRST SECOND THIRD FOURTH ADDRESSCACHE ADDRESS ADDRESS ADDRESS ADDRESS BUS SIZE LINE (MSB) LINE LINE LINE(LSB) 32a 2 Mbyte net4 net4 net4 net4 32b 4 Mbyte net3 net3 net3 net432c 8 Mbyte net2 net2 net3 net4 32d 16 Mbyte  net1 net2 net3 net4

[0020] Still referring to FIG. 3C, microprocessor 50 further comprises aconfiguration register 54. Configuration register 54 provides a controlsignal to multiplexor 53 via a control bus 54 a in response to aselection signal from main logic units 51 via a data bus 51 a. Theselection signal is indicative of a selected cache configuration by mainlogic units 51 during an initial boot of microprocessor 50. The controlsignal is indicative of the address bus that corresponds to the selectedcache configuration. Consequently, multiplexor 53 provides theappropriate address signals via address bus 53 a to SRAM 20 a and SRAM20 b in response to the selection signal. For example, when theselection signal indicates the 8 Mbyte cache has been selected, pin 22 aand pin 26 b concurrently receive address signal net2, pin 26 a and pin22 b concurrently receive address signal net2, pin 23 a and pin 25 bconcurrently receive address signal net3, and pin 23 b and pin 25 aconcurrently receive address signal net4 as indicated by Table 3.

[0021] From the previous description of SRAM 20 a and SRAM 20 b hereinin connection with FIG. 2, one skilled in the art will know how to makeand use electrical couplings between additional synchronous address pinsof SRAM 20 aand SRAM 20 b in accordance with the present invention. Fromthe previous description of microprocessors 30, 40, and 50 in connectionwith FIGS. 3A-3C, respectively, one skilled in the art will know how tomake and use microprocessors in accordance with the present inventionfor selecting a cache configuration between five or more supported cacheconfigurations.

[0022] While the embodiments of the present invention disclosed hereinare presently considered to be preferred, various changes andmodifications can be made without departing from the spirit and scope ofthe invention. The scope of the invention is indicated in the appendedclaims, and all changes that come within the meaning and range ofequivalents are intended to be embraced therein. For examples, the pinconfiguration and size of SRAM 20 a and SRAM 20 b can vary, and/or SRAM20 a and SRAM 20 b may include asynchronous address pins. Additionally,SRAM 20 a and SRAM 20 b may be misaligned along the respective sides ofprocessor card 10, and/or mounted on the same side of processor card 10.Also, other memory devices may be utilized in lieu of SRAM 20 a and SRAM20 b, e.g. dynamic static random access memories.

We claim:
 1. A device, comprising: a processor card; a first memory device mounted upon said processor card, said first memory device including a first address pin and a second address pin; and a second memory device mounted upon said processor card, said second memory device including a third address pin and a fourth address pin, said first address pin and said third address pin being functionally equivalent address pins, said second address pin and said fourth address pin being functionally equivalent address pins, wherein said first address pin and said fourth address pin are electrically coupled to thereby concurrently receive a first address bit signal, and wherein said second address pin and said third address pin are electrically coupled to thereby concurrently receive a second address bit signal.
 2. The device of claim 1, wherein said first memory device is mounted to a front side of said processor card; and said second memory device is mounted to a rear side of said processor card.
 3. The device of claim 2, wherein said first address pin and said fourth address pin are aligned; and said second address pin and said third address pin are aligned.
 4. The device of claim 1, wherein said first memory device is a static random access memory; and said second memory device is a static random access memory.
 5. The device of claim 1, wherein said first memory device further includes a fifth address pin; and said second memory device further includes a sixth address pin, said fifth address pin and said sixth address pin being electrically coupled to thereby concurrently receive a third address bit signal.
 6. The device of claim 5, wherein said fifth address pin and said sixth address pin are functionally dissimilar address pins.
 7. The device of claim 5, wherein said first memory device further includes a seventh address pin; and said second memory device further includes an eighth address pin, said seventh address pin and said eighth address pins being electrically coupled to thereby concurrently receive a fourth address bit signal.
 8. The device of claim 7, wherein said fifth address pin and said eighth address pin are functionally equivalent address pins; and said sixth address pin and said seventh address pin are functionally equivalent address pins.
 9. A system, comprising: a first memory device including a first address pin and a second address pin; a second memory device including a third address pin and a fourth address pin, said first address pin and said third address pin being functionally equivalent address pins, said second address pin and said fourth address pin being functionally equivalent address pins; and a microprocessor operable to concurrently provide a first address bit signal to said first address pin and said fourth address pin, said microprocessor further operable to concurrently provide a second address bit signal to said second address pin and said third address pin.
 10. The system of claim 9, further comprising: a processor card having said first memory device and said second memory device mounted thereon.
 11. The system of claim 10, wherein said first memory device is mounted to a front side of said processor card; and said second memory device is mounted to a rear side of said processor card.
 12. The system of claim 11, wherein said first address pin and said fourth address pin are aligned; and said second address pin and said third address pin are aligned.
 13. The system of claim 9, wherein said first memory device is a static random access memory; and said second memory device is a static random access memory.
 14. The system of claim 9, wherein said first memory device further includes a fifth address pin; said second memory device further includes a sixth address pin; and said microprocessor is further operable to concurrently provide a third address bit signal to said fifth address pin and said sixth address pin.
 15. The system of claim 14, wherein said fifth address pin and said sixth address pin are functionally dissimilar address pins.
 16. The system of claim 14, wherein said first memory device further includes a seventh address pin; said second memory device further includes an eighth address; and said microprocessor is further operable to concurrently provide a fourth address bit signal to said seventh address pin and said eighth address pin.
 17. The system of claim 16, wherein said fifth address pin and said eighth address pin are functionally equivalent address pins; and said sixth address pin and said seventh address pin are functionally equivalent address pins.
 18. The system of claim 9, wherein said microprocessor includes a multiplexor operable to provide said first address bit signal and said second address bit signal in response to a control signal indicative of a cache configuration corresponding to said first address bit signal and said second address bit signal.
 19. The system of claim 14, wherein said microprocessor includes a multiplexor operable to provide said first address bit signal, said second address bit signal, and said third address bit signal in response to a control signal indicative of a cache configuration corresponding to said first address bit signal, said second address bit signal, and said third address bit signal.
 20. The system of claim 16, wherein said microprocessor includes a multiplexor operable to provide said first address bit signal, said second address bit signal, said third address bit signal, and said fourth address bit signal in response to a control signal indicative of a cache configuration corresponding to said first address bit signal, said second address bit signal, said third address bit signal, and said fourth address bit signal.
 21. A method, comprising: operating a microprocessor to generate a first set of at least two address bit signals, said first set of at least two address bit signals being indicative of a first cache configuration; and operating said microprocessor to generate a second set of at least two address bit signals, said second set of at least two address bit signals being indicative of said second cache configuration of said plurality of cache configurations.
 22. The method of claim 21, further comprising: operating a microprocessor to select said first cache configuration of a plurality of cache configurations; operating said microprocessor to provide a control signal indicative of said selection of said first cache configuration; and operating said microprocessor to concurrently provide said first set of at least two address bit signals to a first memory device and a second memory device in response to said control signal.
 23. A method, comprising: operating a microprocessor to select a first cache configuration of a plurality of cache configurations; and subsequently operating said microprocessor to concurrently provide a set of at least two address bit signals to a first memory device and a second memory device, said set of at least two address bit signals being representative of said selection of said first cache configuration.
 24. The method of claim 23, further comprising: operating a microprocessor to provide a control signal indicative of a said selection of a first cache configuration, said operating of said microprocessor to concurrently provide said set of at least two address bit signals to said first memory device and said second memory device is in response to said control signal.
 25. A method, comprising: providing a processor board including a first conductor and a second conductor; providing a first memory device including a first address pin and a second address pin; providing a second memory device including a third address pin and a fourth address pin, said first address pin and said fourth address pin being functionally equivalent address pins, said second address pin and said third address pin being functionally equivalent address pin; mounting said first memory device on said processor card, said first address pin contacting said first conductor, said second address pin contacting said second conductor; mounting a second memory device said processor card, said third address pin contacting said first conductor whereby said first address pin and said third address pin are electrically coupled, said fourth address pin contacting said second conductor whereby said second address pin and said fourth address pin are electrically coupled.
 26. The method of claim 25, wherein said mounting of said first memory device on said processor card includes mounting first memory device said mounted on a front side of said processor card, and said mounting of said second memory device on said processor card includes mounting said second memory device said mounted on a rear side of said processor card.
 27. The method of claim 26, wherein said mounting of said second memory device said on said processor card includes aligning said first address pin and said third address pin and aligning said second address pin and fourth address pin are aligned. 